Write-up in progress
Binary Sudoku was implemented on a Mojo FPGA with programmable LED output and game-state logic in hardware.
A complete post will cover constraint encoding, control flow in HDL, and observability during board-level debugging.
This post is a draft and is not listed publicly.
· 1 min read
Binary Sudoku
8x8 Binary Sudoku implemented on a Mojo FPGA with constraint logic in hardware and WS2812b LED output.
fpga · hardware · digital-design · hdl · draft